Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits | Journal of Applied Research and Technology. JART

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"cabecera" => "Original" "titulo" => "Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits" "tieneTextoCompleto" => true "paginas" => array:1 [ 0 => array:2 [ "paginaInicial" => "233" "paginaFinal" => "241" ] ] "autores" => array:1 [ 0 => array:4 [ "autoresLista" => "Mohammad Hossein Moaiyeri, Afshin Rahi, Fazel Sharifi, Keivan Navi" "autores" => array:4 [ 0 => array:4 [ "nombre" => "Mohammad Hossein" "apellidos" => "Moaiyeri" "email" => array:1 [ 0 => "h_moaiyeri@sbu.ac.ir" ] "referencia" => array:1 [ 0 => array:2 [ "etiqueta" => "*" "identificador" => "cor0005" ] ] ] 1 => array:2 [ "nombre" => "Afshin" "apellidos" => "Rahi" ] 2 => array:2 [ "nombre" => "Fazel" "apellidos" => "Sharifi" ] 3 => array:2 [ "nombre" => "Keivan" "apellidos" => "Navi" ] ] "afiliaciones" => array:1 [ 0 => array:2 [ "entidad" => "Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran 1983963113, Iran" "identificador" => "aff0005" ] ] "correspondencia" => array:1 [ 0 => array:3 [ "identificador" => "cor0005" "etiqueta" => "⁎" "correspondencia" => "Corresponding author." ] ] ] ] "resumenGrafico" => array:2 [ "original" => 0 "multimedia" => array:7 [ "identificador" => "fig0010" "etiqueta" => "Fig. 2" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr2.jpeg" "Alto" => 1922 "Ancho" => 2446 "Tamanyo" => 272032 ] ] "descripcion" => array:1 [ "en" => "CNTFET-based quaternary Mux (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri, Navi, et al., 2012</a>). (a) Quaternary decoder. (b) TG network." ] ] ] "textoCompleto" => "1IntroductionIn recent years, nanoscale CMOSes have encountered some challenges with respect to design and manufacturing such as increased leakage currents, decreased gate control and degraded I–V characteristics. Modern nanotechnologies have been introduced for implementing nanoscale circuits such as quantum-dot cellular automata (QCA), single electron transistor (SET), and carbon nanotube field effect transistor (CNTFET) to resolve such challenges. Low power consumption, ballistic transport under low supply voltage, and small dimensions are among the features of such nano-devices for designing ultra-low-power and ultra-high-density integrated circuits (<a class="elsevierStyleCrossRefs" href="#bib0005">Abu El-Seoud, El-Banna, & Hakim, 2007; Keshavarzian & Navi, 2009; Keshavarzian & Sarikhani, 2013; Raychowdhury & Roy, 2005; Tehrani, Safaei, Moaiyeri, & Navi, 2011</a>). Meanwhile, CNTFET can be considered as the best alternative for MOSFET-based circuits as it has higher resemblance with MOSFET and offers a high current gain (<a class="elsevierStyleCrossRef" href="#bib0070">Moaiyeri, Faghih Mirzaee, Navi, & Momeni, 2012a</a>).Multiple-valued logic (MVL) circuits have gained more attention in CNTFET technology during the recent years as they are suitable devices for designing MVL circuits with multiple threshold voltages. Multiple threshold voltages can be provided by adopting the required diameters for the nanotubes of a CNTFET (<a class="elsevierStyleCrossRef" href="#bib0055">Lin, Kim, & Lombard, 2012</a>).The recent VLSI chips are faced with difficulties in placement and routing of the logic blocks and very large area of interconnects. Moreover, the pin-out constraint limits the number of connections of an integrated circuit with the external world and makes the packaging process more complicated. In addition, implementing many complex applications such as process control and decision systems is usually useless and impractical in binary logic.In order to resolve these problems, digital systems using radices greater than two and multiple-valued logic (MVL) circuits should be taken into account. MVL systems work with more than two allowed logics. It is worth noting that the four-level logic (quaternary logic) benefits from ease of conversion between quaternary signals and binary signals which are produced by the existing binary circuits.By utilizing MVL instead of binary logic the data content per interconnection is increased which reduces the number of wires. Also, pins of chips carry more information which decreases the number of required pins. In addition, MVL provides considerably more information compaction on logic circuits which has been successfully carried out in very dense flash memories, where a single memory cell can hold numerous logic values.In arithmetic circuits, redundant number systems can reduce or even omit the rippling carries that leads to faster arithmetic operations as compared to the normal binary logic. Moreover, MVL can be even applied to solve the binary problems more effectively. For instance, a third logic value can be utilized as a medium for signaling the faulty operation in testing the binary circuits (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri, Navi, & Hashemipour, 2012b</a>).Different methods for designing MVL circuits have been presented so far in the literature. However, most of them suffer from some critical drawbacks. For instance, the designs of (<a class="elsevierStyleCrossRefs" href="#bib0080">Mouftah & Jordan, 1974; Mouftah & Smith, 1982; Raychowdhury & Roy, 2005</a>) need very large resistors. The CNTFET-based quaternary logic gates presented in (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al., 2012b</a>) function based on resistive voltage division at the output CNTFET stage which considerably increases the power consumption. However, the output drivers of these circuits enhance their drivability and considerably reduce the propagation delay. Efficient multiple-valued logic gates have been presented in (<a class="elsevierStyleCrossRef" href="#bib0045">Liang, Chen, Han, & Lombardi, 2014</a>) based on the pseudo n-type method which reduces the design complexity. However, the ratioed logic of the pseudo n-type method leads to higher propagation delay and power consumption and consequently less energy efficiency. In addition, it reduces the output logic swing that also increases the delay and static power consumption and degrades the robustness when these gates drive next stages. Moreover, in general, each quaternary function can be implemented using quaternary multiplexers (<a class="elsevierStyleCrossRef" href="#bib0010">Datla, 2009</a>). However, purely multiplexer-based design does not result in a hardware-efficient circuit.In this paper, robust and energy-efficient CNTFET-based quaternary minimum and maximum circuits are designed for nanoelectronics based on an innovative combination of quaternary multiplexer, threshold detectors and specific ternary buffers.In the remainder of the paper, in Section <a class="elsevierStyleCrossRef" href="#sec0010">2</a> the CNTFET device is briefly reviewed. In Section <a class="elsevierStyleCrossRef" href="#sec0015">3</a> the proposed designs are presented. The simulation results are represented in Section <a class="elsevierStyleCrossRef" href="#sec0020">4</a> and finally Section <a class="elsevierStyleCrossRef" href="#sec0025">5</a> concludes the paper.2Carbon nanotube field effect transistor (CNTFET)Carbon nanotubes (CNTs) are graphite cylindrical sheets, which are categorized into two groups: single-walled carbon nanotubes (SWCNTs) that are made of a cylinder; and multi-walled carbon nanotubes (MWCNTs) that are made of more than a cylinder (<a class="elsevierStyleCrossRef" href="#bib0060">McEuen, Fuhrer, & Park, 2002</a>). There is a chirality vector for any carbon nanotube, which is specified by a pair (n, m) and determines the angle of carbon atom formation along the nanotube. Specifications of nanotubes depend on their structure and they can act as metal or semiconductor depending on the chirality. If (K∈ℤ) n−m≠3K, the SWCNT is semiconductor and otherwise, the SWCNT is metal. SWCNTs are used instead of silicon bulk in the channel of transistors as the channel substance of CNTFET devices, which reduces and sometimes removes many undesired parasitic elements. Electrons and holes do not have an identical mobility in silicon whereas n-type and p-type CNTFETs have similar mobility (μN=μp). This feature of CNTFETs facilitates the transistor sizing, as the complexities will be fewer than the ones of MOSFET-based design. CNTFET nanodevice has similar I–V characteristics as compared with a well-tempered MOSFET, which is another advantage of CNTFETs (<a class="elsevierStyleCrossRef" href="#bib0065">Moaiyeri, Doostaregan, & Navi, 2011</a>).CNTFETs have three types including Schottky barrier CNTFET (SB-CNTFET), tunneling CNTFET (T-CNTFET) and MOSFET-like-CNTFET (<a class="elsevierStyleCrossRef" href="#bib0095">Raychowdhury & Roy, 2007</a>). However, the MOSFET-like CNTFET is more suitable for designing circuits based on the CMOS style because of their inherent electrical characteristics and transistor structure. Another feature of the MOSFET-like CNTFET is that drain/source-channel connections have no Schottky barrier and it has a considerably higher ON current. <a class="elsevierStyleCrossRef" href="#fig0005">Figure 1</a> shows a MOSFET-like CNTFET structure.<elsevierMultimedia ident="fig0005"></elsevierMultimedia>According to <a class="elsevierStyleCrossRef" href="#fig0005">Figure 1</a>, the distance between the centers of two adjacent nanotubes is called pitch, which has a direct impact on the width of the connections and gate of the transistor. The width of the gate of a CNTFET is estimated by the following equation (<a class="elsevierStyleCrossRef" href="#bib0040">Kim, Kim, & Lombardi, 2009</a>):<elsevierMultimedia ident="eq0005"></elsevierMultimedia>where N is the number of nanotubes under the gate, Wmin is the minimum width of the gate determined by the photolithography process and DCNT is the diameter of carbon nanotube, which is calculated as given in Eq. <a class="elsevierStyleCrossRef" href="#eq0010">(2)</a>, where, a≈0.249nm is the lattice constant in a CNT structure (<a class="elsevierStyleCrossRef" href="#bib0040">Kim et al., 2009</a>):<elsevierMultimedia ident="eq0010"></elsevierMultimedia>The threshold voltage (Vth) of a CNTFET can be determined by adopting proper CNT diameters, which is obtained from Eq. <a class="elsevierStyleCrossRef" href="#eq0015">(3)</a> (<a class="elsevierStyleCrossRef" href="#bib0040">Kim et al., 2009</a>):<elsevierMultimedia ident="eq0015"></elsevierMultimedia>where e is the unit electron charge, Eg is the CNT band gap, Eπ (≈3.033eV) is the energy bond of carbon π–π in the tight bonding model.Many feasible and effective approaches have already been presented in the literature for growing CNTs with a specified chirality and determining the desired threshold voltage for multi-tube CNTFETs (<a class="elsevierStyleCrossRefs" href="#bib0050">Lin et al., 2009; Yang et al., 2014</a>). Nevertheless, designing CNTFET-based circuits with fewer number of required CNT reduces fabrication costs and enhance the manufacturability.3The proposed quaternary circuitsAs minimum (logical multi-valued AND) and max (logical multi-valued OR) operators are the most fundamental blocks of multiple valued logic systems, an appropriate design of these two operators can be effective in enhancing the performance and energy-efficiency of MVL systems. In this paper a new method for designing energy-efficient quaternary logic circuits is proposed.The proposed method utilizes a quaternary 4-to-1 multiplexer (QMux) consisting of a selector (generated by a quaternary decoder) and a quaternary transmission gate network (QTG) and also threshold detector (TD) circuits. An efficient design for CNTFET-based quaternary multiplexer has been presented in (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al., 2012b</a>), which is shown in <a class="elsevierStyleCrossRef" href="#fig0010">Figure 2</a>.<elsevierMultimedia ident="fig0010"></elsevierMultimedia><a class="elsevierStyleCrossRef" href="#fig0015">Figure 3</a>(a) and (b) show the basic schema of the proposed quaternary minimum and maximum circuits, respectively. In these two circuits, the QMux shown in <a class="elsevierStyleCrossRef" href="#fig0010">Figure 2</a> is used as the main body of the circuit. The four inputs of the QMux circuits are assigned as per <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a>, and accordingly the output of QMux1 will be the quaternary minimum signal (QMin) or the quaternary maximum signal (QMax).<elsevierMultimedia ident="fig0015"></elsevierMultimedia><elsevierMultimedia ident="tbl0005"></elsevierMultimedia>As <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a> shows, input a can be used as a selector in QMux1. Therefore, it is possible to divide the table into 4 sections based on different logic levels of a and adjust each input of QMux1 for each section of the table. To adjust QMux1 input pins in QMin circuit, we act as follows:In the first section (a=0), the QMin output has always a zero logic. Therefore, it is possible to connect the first QMux1 pin to zero logic without using any intermediate.In the second section (a=1), the QMin output has 0 and 1 logics. According to the table, if b=0, QMin equals 0. Otherwise (b≠0), QMin equals to 1. Therefore, an nMOS-based threshold detector (TDN) module can be used, which is switched on logical ‘0.5’ and is controlled by the input signal b through the inverters (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al., 2012b</a>). <a class="elsevierStyleCrossRef" href="#fig0020">Figure 4</a> shows the nMOS-based TD circuit.<elsevierMultimedia ident="fig0020"></elsevierMultimedia>In the third section (a=2), QMin output has 0, 1, 2 and 2 logics, respectively. In order to realize these logics in the third QMux1 input pin, another multiplexer (QMux2) with input selector b can be used. Accordingly, the inputs of QMux2 should be connected to 0, 1, 2, 2 logics.In the fourth section (a=3), the QMin output is similar to input b. Therefore, it is possible to connect the fourth QMux1 input pin to the input b without using any intermediate.To adjust QMux1 input pins in maximum circuit, we act as follows:<ul class="elsevierStyleList" id="lis0005"><li class="elsevierStyleListItem" id="lsti0005">In the first section (a=0), the QMax output is similar to input b. Therefore, it is possible to connect the first QMux1 pin to the input b without using any intermediate.</li><li class="elsevierStyleListItem" id="lsti0010">In the second section (a=1), the QMax output has 1, 1, 2 and 3 logics, respectively. To realize these logics in the second input of QMux1, another multiplexer (QMux2) with a b input selector can be used. Inputs of the multiplexer can be respectively connected to 1, 1, 2 and 3 logics.</li><li class="elsevierStyleListItem" id="lsti0015">In the third section (a=2), QMax output has 2 and 3 logics. As <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a> shows, for b≠3, the output of QMax equals to logic 2 and for input b=3, output logic equals to 3. Therefore, a pMOS-based TD (TDP) module can be used, which switches on logic ‘2.5’ and controlled by the input signal b through the inverters. <a class="elsevierStyleCrossRef" href="#fig0025">Figure 5</a> shows the proposed pMOS-based TD.<elsevierMultimedia ident="fig0025"></elsevierMultimedia></li><li class="elsevierStyleListItem" id="lsti0020">In the fourth section (a=3), QMax output has always logic 3. Therefore, it is possible to connect the fourth QMux1 pin to logic 3 without using any intermediate.</li></ul>The proposed design can be simplified more by removing the QMux2 module used in the second pin of maximum circuit and the third pin of minimum circuit and replacing each of them by another circuit in order to reach a more hardware-efficient circuit with higher performance. Therefore, two ternary buffer circuits are designed, which can help to achieve the desired outputs with lower number of transistors. As the QMux2 module has been utilized with different inputs in the basic schemas of the proposed minimum and maximum circuits, two different ternary buffers should be used in the second design for minimum and maximum circuits. The main difference between these two buffers is their different required switching thresholds which are obtained by adopting proper diameters in the first level inverters of the buffers.<a class="elsevierStyleCrossRef" href="#fig0030">Figure 6</a> shows the final proposed minimum circuit and the transistor level schema of its ternary buffer (TB1). This circuit includes specific CMOS-like threshold detector inverters and a voltage division stage according to (<a class="elsevierStyleCrossRef" href="#bib0065">Moaiyeri et al., 2011</a>). It is worth pointing out that in the proposed TB1 circuit DN=1.018nm and DP=1.487nm are adopted for the diameters of the n-type and p-type devices in inverter1 and DN=1.487nm and DP=0.783nm are adopted in inverter2. In addition, a 2/3VDD (a 2 logical level) voltage is utilized as the supply in this circuit. Accordingly, the required 0, 1, 2 logics are obtained at the output of TB1 in the proposed minimum circuit.<elsevierMultimedia ident="fig0030"></elsevierMultimedia>The voltage transfer characteristic (VTC) curve of the ternary buffer used in the proposed QMin circuit is illustrated in <a class="elsevierStyleCrossRef" href="#fig0035">Figure 7</a>. As demonstrated in <a class="elsevierStyleCrossRef" href="#fig0035">Figure 7</a>, the proposed buffer produces the desired output voltage levels including 0, 1/3VDD and 2/3VDD (VDD=0.8V). In addition, it has a near-ideal VTC with quite steep transition regions which enhance the robustness of the design.<elsevierMultimedia ident="fig0035"></elsevierMultimedia><a class="elsevierStyleCrossRef" href="#fig0040">Figure 8</a> shows the final proposed maximum circuit and the transistor level schema of its ternary buffer (TB2). It is worth pointing out that by selecting DN=1.487nm and DP=0.783nm for the diameters of the n-type and p-type devices in Inverter1 and DN=0.783nm and DP=1.018nm in Inverter2 and using a 1/3VDD supply (a 1 logical value) as the lowest voltage level, the required 1, 2, 3 logics are obtained in TB2 of the maximum circuit.<elsevierMultimedia ident="fig0040"></elsevierMultimedia>The voltage transfer characteristic curve of the ternary buffer used in the proposed QMax circuit is shown in <a class="elsevierStyleCrossRef" href="#fig0045">Figure 9</a>. As illustrated in <a class="elsevierStyleCrossRef" href="#fig0045">Figure 9</a>, the proposed buffer produces the desired output voltage levels including 1/3VDD, 2/3VDD and VDD. In addition, it has a near-ideal VTC with quite steep transition regions which enhance the robustness of the design.<elsevierMultimedia ident="fig0045"></elsevierMultimedia>4Simulation results and comparisonThis section discusses the performance of the proposed circuits in different conditions using Synopsys HSPICE with the Stanford compact model CNTFET including all the possible non-idealities at 32nm technology node. This standard model has been developed for unipolar enhancement-mode MOSFET-like-CNTFET, devices in which each transistor may include one or more CNTs as its channel. This model considers the following items idealistically. The Schottky barrier effects at the contacts, inter-CNT charge screening effects, scattering, back-gate effect, gate and source/drain resistances and expansion of doped regions of source/drain (<a class="elsevierStyleCrossRefs" href="#bib0015">Deng, 2007; Deng & Wong, 2007a, 2007b</a>). <a class="elsevierStyleCrossRef" href="#tbl0010">Table 2</a> shows CNTFET model parameters, their values, and a brief explanation.<elsevierMultimedia ident="tbl0010"></elsevierMultimedia><a class="elsevierStyleCrossRef" href="#fig0050">Figure 10</a> shows the input and output signals of the proposed quaternary logic circuits simulated at 0.8V supply voltage, which authenticates the correct operation of the designs.<elsevierMultimedia ident="fig0050"></elsevierMultimedia>The proposed CNTFET-based quaternary circuits are simulated at 0.8V supply voltage with a 0.5fF load capacitor and the results including propagation delay, power consumption, power-delay product (PDP) and energy-delay product (EDP) are given in <a class="elsevierStyleCrossRef" href="#tbl0015">Table 3</a>. According to the results, the proposed designs have smaller propagation delays as compared to (<a class="elsevierStyleCrossRef" href="#bib0045">Liang et al., 2014</a>), lower power consumption in comparison with (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al., 2012b</a>) and the lowest PDP and EDP values.<elsevierMultimedia ident="tbl0015"></elsevierMultimedia>Moreover, the proposed designs are simulated at different ambient temperatures from 0 to 90°C in order to evaluate their operation at different temperatures. The PDP of a CNTFET-based circuit usually does not change significantly by temperature variations because of CNT thermal stability. In addition, as shown in <a class="elsevierStyleCrossRef" href="#fig0055">Figure 11</a>, the proposed designs have lower PDP at different temperatures as compared to the other designs.<elsevierMultimedia ident="fig0055"></elsevierMultimedia>Systematic and random process variations are among the major challenges ahead of nanoscale devices and circuits. As the proposed CNTFET-based quaternary logic circuits are designed based on multiple threshold voltage method, the impact of the process variation that alternates the threshold voltage of the CNTFETs should be definitely studied. As the proposed method is based on multi threshold CNTFETs and the threshold voltage of a CNTFET is dominantly determined by the diameter of its CNTs, the functionality of the proposed quaternary circuit should be evaluated considering CNT diameter variations. In addition, recently, CNT counts variations is proven experimentally to be the most important source of variation in CNTFET circuits (<a class="elsevierStyleCrossRef" href="#bib0110">Zhang, Patil, Wong, & Mitra, 2011</a>).Therefore, the Monte Carlo simulation has been carried out to assess these process variations with ±5% up to ±15% Gaussian distributions and variation at the ±3σ level. <a class="elsevierStyleCrossRef" href="#fig0060">Figure 12</a> shows the results of this simulation. According to the results, the proposed CNTFET-based logic circuits are very low sensitive to process variations, especially in terms of power variations.<elsevierMultimedia ident="fig0060"></elsevierMultimedia>5ConclusionsAs the nanotechnology-based multiple-valued logic design is concerned, energy-efficient min–max circuits have been proposed based on CNTFETs with multi threshold voltages based on the CNTFET's unique properties. The simulation results certify authenticity of the proposed method as a superior proposed quaternary minimum and maximum circuit, especially in terms of PDP and EDP, as compared with other circuits under different simulation conditions and in the presence of process and temperature variations. The proposed designs leads to 51% and 63% lower PDP and 64% and 61% lower EDP, respectively as compared to the state-of-the-art CNTFET-based quaternary circuits presented in the literature. In future work we expect to develop the proposed method for implementing complex arithmetic operations and designing an efficient quaternary ALU. Also, we expect that the proposed method can be generalized effectively for radices higher than four.Conflict of interestThe authors have no conflicts of interest to declare." "textoCompletoSecciones" => array:1 [ "secciones" => array:9 [ 0 => array:3 [ "identificador" => "xres856035" "titulo" => "Abstract" "secciones" => array:1 [ 0 => array:1 [ "identificador" => "abst0005" ] ] ] 1 => array:2 [ "identificador" => "xpalclavsec850104" "titulo" => "Keywords" ] 2 => array:2 [ "identificador" => "sec0005" "titulo" => "Introduction" ] 3 => array:2 [ "identificador" => "sec0010" "titulo" => "Carbon nanotube field effect transistor (CNTFET)" ] 4 => array:2 [ "identificador" => "sec0015" "titulo" => "The proposed quaternary circuits" ] 5 => array:2 [ "identificador" => "sec0020" "titulo" => "Simulation results and comparison" ] 6 => array:2 [ "identificador" => "sec0025" "titulo" => "Conclusions" ] 7 => array:2 [ "identificador" => "sec0070" "titulo" => "Conflict of interest" ] 8 => array:1 [ "titulo" => "References" ] ] ] "pdfFichero" => "main.pdf" "tienePdf" => true "fechaRecibido" => "2015-07-31" "fechaAceptado" => "2016-12-09" "PalabrasClave" => array:1 [ "en" => array:1 [ 0 => array:4 [ "clase" => "keyword" "titulo" => "Keywords" "identificador" => "xpalclavsec850104" "palabras" => array:4 [ 0 => "Carbon nanotube field effect transistor (CNTFET)" 1 => "Quaternary logic" 2 => "Minimum/maximum circuits" 3 => "Nanoelectronics" ] ] ] ] "tieneResumen" => true "resumen" => array:1 [ "en" => array:2 [ "titulo" => "Abstract" "resumen" => "This article presents energy-efficient quaternary minimum and maximum logic circuits based on carbon nanotube field-effect transistor (CNTFET). The specific features of CNTFET, such as the possibility of determining the desired threshold voltages which are obtained by acquiring suitable diameters for carbon nanotubes, facilitate designing efficient circuits with multiple threshold voltages. The proposed minimum and maximum circuits are designed using an efficient combination of quaternary multiplexers and specific ternary buffers. The proposed designs are simulated using Synopsys HSPICE with the Stanford 32nm CNTFET technology and the performance parameters and sensitivity to process and temperature variations are evaluated through comprehensive simulations. The results demonstrate that the proposed QMin and QMax designs operate with high robustness even in the presence of major process variations. In addition, they have 51% and 63% lower power-delay product (PDP) and 64% and 61% lower energy-delay product (EDP), respectively, as compared to the state-of-the-art CNTFET-based quaternary circuits recently presented in the literature." ] ] "NotaPie" => array:1 [ 0 => array:1 [ "nota" => "Peer Review under the responsibility of Universidad Nacional Autónoma de México." ] ] "multimedia" => array:18 [ 0 => array:7 [ "identificador" => "fig0005" "etiqueta" => "Fig. 1" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr1.jpeg" "Alto" => 959 "Ancho" => 1623 "Tamanyo" => 106601 ] ] "descripcion" => array:1 [ "en" => "Schematic diagram of a MOSFET-like CNTFET." ] ] 1 => array:7 [ "identificador" => "fig0010" "etiqueta" => "Fig. 2" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr2.jpeg" "Alto" => 1922 "Ancho" => 2446 "Tamanyo" => 272032 ] ] "descripcion" => array:1 [ "en" => "CNTFET-based quaternary Mux (<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri, Navi, et al., 2012</a>). (a) Quaternary decoder. (b) TG network." ] ] 2 => array:7 [ "identificador" => "fig0015" "etiqueta" => "Fig. 3" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr3.jpeg" "Alto" => 829 "Ancho" => 1309 "Tamanyo" => 46013 ] ] "descripcion" => array:1 [ "en" => "The basic schematic of the proposed quaternary two-input logic circuits. (a) Quaternary min. (b) Quaternary max." ] ] 3 => array:7 [ "identificador" => "fig0020" "etiqueta" => "Fig. 4" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr4.jpeg" "Alto" => 688 "Ancho" => 1542 "Tamanyo" => 61293 ] ] "descripcion" => array:1 [ "en" => "The TD circuit based on n-type switches (TDN)." ] ] 4 => array:7 [ "identificador" => "fig0025" "etiqueta" => "Fig. 5" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr5.jpeg" "Alto" => 709 "Ancho" => 1667 "Tamanyo" => 69160 ] ] "descripcion" => array:1 [ "en" => "The TD circuit based on p-type switches (TDP)." ] ] 5 => array:7 [ "identificador" => "fig0030" "etiqueta" => "Fig. 6" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr6.jpeg" "Alto" => 1767 "Ancho" => 1667 "Tamanyo" => 99455 ] ] "descripcion" => array:1 [ "en" => "The proposed quaternary minimum circuit." ] ] 6 => array:7 [ "identificador" => "fig0035" "etiqueta" => "Fig. 7" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr7.jpeg" "Alto" => 1358 "Ancho" => 1544 "Tamanyo" => 44497 ] ] "descripcion" => array:1 [ "en" => "The VTC of the first ternary buffer (TB1) used in QMin." ] ] 7 => array:7 [ "identificador" => "fig0040" "etiqueta" => "Fig. 8" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr8.jpeg" "Alto" => 1805 "Ancho" => 1667 "Tamanyo" => 102251 ] ] "descripcion" => array:1 [ "en" => "The proposed quaternary maximum circuit." ] ] 8 => array:7 [ "identificador" => "fig0045" "etiqueta" => "Fig. 9" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr9.jpeg" "Alto" => 1337 "Ancho" => 1563 "Tamanyo" => 49696 ] ] "descripcion" => array:1 [ "en" => "The VTC of the second ternary buffer (TB2) used in QMax." ] ] 9 => array:7 [ "identificador" => "fig0050" "etiqueta" => "Fig. 10" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr10.jpeg" "Alto" => 1257 "Ancho" => 1667 "Tamanyo" => 116506 ] ] "descripcion" => array:1 [ "en" => "Transient response of the proposed designs." ] ] 10 => array:7 [ "identificador" => "fig0055" "etiqueta" => "Fig. 11" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr11.jpeg" "Alto" => 2829 "Ancho" => 1589 "Tamanyo" => 207673 ] ] "descripcion" => array:1 [ "en" => "The PDP variation of designs versus temperature variations." ] ] 11 => array:7 [ "identificador" => "fig0060" "etiqueta" => "Fig. 12" "tipo" => "MULTIMEDIAFIGURA" "mostrarFloat" => true "mostrarDisplay" => false "figura" => array:1 [ 0 => array:4 [ "imagen" => "gr12.jpeg" "Alto" => 4216 "Ancho" => 2599 "Tamanyo" => 714982 ] ] "descripcion" => array:1 [ "en" => "The parameter variations of the designs in the presence of process variations." ] ] 12 => array:8 [ "identificador" => "tbl0005" "etiqueta" => "Table 1" "tipo" => "MULTIMEDIATABLA" "mostrarFloat" => true "mostrarDisplay" => false "detalles" => array:1 [ 0 => array:3 [ "identificador" => "at1" "detalle" => "Table " "rol" => "short" ] ] "tabla" => array:1 [ "tablatextoimagen" => array:1 [ 0 => array:2 [ "tabla" => array:1 [ 0 => """ <table border="0" frame="\n \t\t\t\t\tvoid\n \t\t\t\t" class=""><thead title="thead"><tr title="table-row"><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">a \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">b \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Min \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Max \t\t\t\t\t\t\n \t\t\t\t</th></tr></thead><tbody title="tbody"><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry 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title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " colspan="4" align="left" valign="top"></td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " colspan="4" align="left" valign="top"></td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3 \t\t\t\t\t\t\n \t\t\t\t</td></tr></tbody></table> """ ] "imagenFichero" => array:1 [ 0 => "xTab1446118.png" ] ] ] ] "descripcion" => array:1 [ "en" => "The truth table of the QMin and QMax operations." ] ] 13 => array:8 [ "identificador" => "tbl0010" "etiqueta" => "Table 2" "tipo" => "MULTIMEDIATABLA" "mostrarFloat" => true "mostrarDisplay" => false "detalles" => array:1 [ 0 => array:3 [ "identificador" => "at2" "detalle" => "Table " "rol" => "short" ] ] "tabla" => array:1 [ "tablatextoimagen" => array:1 [ 0 => array:2 [ "tabla" => array:1 [ 0 => """ <table border="0" frame="\n \t\t\t\t\tvoid\n \t\t\t\t" class=""><thead title="thead"><tr title="table-row"><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Parameter \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Brief description \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Value \t\t\t\t\t\t\n \t\t\t\t</th></tr></thead><tbody title="tbody"><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Lch \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">Physical channel length \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">32nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Lss \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The length of doped CNT source-side extension region \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">32nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Ldd \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The length of doped CNT drain-side extension region \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">32nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Lgeff \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The Scattering mean free path in the intrinsic CNT channel and S/D regions \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">100nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Pitch \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The distance between the centers of two neighboring CNTs within the same device \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">20nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Leff \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The mean free path in p+/n+ doped CNT \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">15nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Sub_pitch \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">Sub-lithographic (e.g. CNT gate width) pitch \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">4nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Kox \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The dielectric constant of high-k top gate dielectric material(HfO2) \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">16 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Lox \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The thickness of high-k top gate dielectric material \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">4nm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Ksub \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The dielectric constant of substrate (SiO2) \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">4 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Csub \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The coupling capacitance between the channel region and the substrate (SiO2) \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">40aF/μm \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Efi \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The Fermi level of the doped S/D tube \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">6eV \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Phi_M \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">The work function of source/drain metal contact \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">4.6eV \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Phi_S \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">CNT work function \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="left" valign="top">4.5eV \t\t\t\t\t\t\n \t\t\t\t</td></tr></tbody></table> """ ] "imagenFichero" => array:1 [ 0 => "xTab1446117.png" ] ] ] ] "descripcion" => array:1 [ "en" => "Some of the important CNTFET model parameters." ] ] 14 => array:8 [ "identificador" => "tbl0015" "etiqueta" => "Table 3" "tipo" => "MULTIMEDIATABLA" "mostrarFloat" => true "mostrarDisplay" => false "detalles" => array:1 [ 0 => array:3 [ "identificador" => "at3" "detalle" => "Table " "rol" => "short" ] ] "tabla" => array:1 [ "tablatextoimagen" => array:1 [ 0 => array:2 [ "tabla" => array:1 [ 0 => """ <table border="0" frame="\n \t\t\t\t\tvoid\n \t\t\t\t" class=""><thead title="thead"><tr title="table-row"><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Designs \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Delay (10−12s) \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Power (10−6W) \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">PDP (10−16J) \t\t\t\t\t\t\n \t\t\t\t</th><th class="td" title="table-head " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">EDP (10−27Js) \t\t\t\t\t\t\n \t\t\t\t</th></tr></thead><tbody title="tbody"><tr title="table-row"><td class="td" title="table-entry " colspan="5" align="left" valign="top">QMin</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Proposed design \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">35.91 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1.401 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.503 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1.806 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Design of <a class="elsevierStyleCrossRef" href="#bib0045">Liang et al. (2014)</a> \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">138.1 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.451 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.623 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">8.601 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Design of <a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri, Navi, et al. (2012b)</a> \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">11.96 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">24.57 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2.931 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">3.504 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry " colspan="5" align="left" valign="top"></td></tr><tr title="table-row"><td class="td" title="table-entry " colspan="5" align="left" valign="top">QMax</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Proposed design \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">32.44 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1.350 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.436 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">1.414 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Design of <a class="elsevierStyleCrossRef" href="#bib0045">Liang et al. (2014)</a> \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">130.8 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.621 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">0.811 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">10.61 \t\t\t\t\t\t\n \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Design of <a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri, Navi, et al. (2012b)</a> \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">9.741 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">24.58 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2.239 \t\t\t\t\t\t\n \t\t\t\t</td><td class="td" title="table-entry " align="char" valign="top">2.181 \t\t\t\t\t\t\n \t\t\t\t</td></tr></tbody></table> """ ] "imagenFichero" => array:1 [ 0 => "xTab1446119.png" ] ] ] ] "descripcion" => array:1 [ "en" => "Simulation result of quaternary maximum and minimum circuits." ] ] 15 => array:6 [ "identificador" => "eq0005" "etiqueta" => "(1)" "tipo" => "MULTIMEDIAFORMULA" "mostrarFloat" => false "mostrarDisplay" => true "Formula" => array:5 [ "Matematica" => "Wgate=max(Wmin,N×Pitch)" "Fichero" => "STRIPIN_si2.jpeg" "Tamanyo" => 1779 "Alto" => 17 "Ancho" => 208 ] ] 16 => array:6 [ "identificador" => "eq0010" "etiqueta" => "(2)" "tipo" => "MULTIMEDIAFORMULA" "mostrarFloat" => false "mostrarDisplay" => true "Formula" => array:5 [ "Matematica" => "DCNT=an2+m2+nmπ≈0.0783n2+m2+nm" "Fichero" => "STRIPIN_si3.jpeg" "Tamanyo" => 3768 "Alto" => 38 "Ancho" => 363 ] ] 17 => array:6 [ "identificador" => "eq0015" "etiqueta" => "(3)" "tipo" => "MULTIMEDIAFORMULA" "mostrarFloat" => false "mostrarDisplay" => true "Formula" => array:5 [ "Matematica" => "Vth≈Eg2e=33aEπeDCNT≃0.436DCNT(nm)" "Fichero" => "STRIPIN_si4.jpeg" "Tamanyo" => 3510 "Alto" => 41 "Ancho" => 257 ] ] ] "bibliografia" => array:2 [ "titulo" => "References" "seccion" => array:1 [ 0 => array:2 [ "identificador" => "bibs0005" "bibliografiaReferencia" => array:22 [ 0 => array:3 [ "identificador" => "bib0005" "etiqueta" => "Abu El-Seoud et al., 2007" "referencia" => array:1 [ 0 => array:2 [ "contribucion" => array:1 [ 0 => array:2 [ "titulo" => "On modelling and characterization of single electron transistor" "autores" => array:1 [ 0 => array:2 [ "etal" => false "autores" => array:3 [ 0 => "A.K. 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Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits

Mohammad Hossein Moaiyeri

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h_moaiyeri@sbu.ac.ir

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, Afshin Rahi, Fazel Sharifi, Keivan Navi

Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran 1983963113, Iran

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2012</a>&#41;&#46;</p><p id="par0015" class="elsevierStylePara elsevierViewall">The recent VLSI chips are faced with difficulties in placement and routing of the logic blocks and very large area of interconnects&#46; Moreover&#44; the pin-out constraint limits the number of connections of an integrated circuit with the external world and makes the packaging process more complicated&#46; In addition&#44; implementing many complex applications such as process control and decision systems is usually useless and impractical in binary logic&#46;</p><p id="par0020" class="elsevierStylePara elsevierViewall">In order to resolve these problems&#44; digital systems using radices greater than two and multiple-valued logic &#40;MVL&#41; circuits should be taken into account&#46; MVL systems work with more than two allowed logics&#46; It is worth noting that the four-level logic &#40;quaternary logic&#41; benefits from ease of conversion between quaternary signals and binary signals which are produced by the existing binary circuits&#46;</p><p id="par0025" class="elsevierStylePara elsevierViewall">By utilizing MVL instead of binary logic the data content per interconnection is increased which reduces the number of wires&#46; Also&#44; pins of chips carry more information which decreases the number of required pins&#46; In addition&#44; MVL provides considerably more information compaction on logic circuits which has been successfully carried out in very dense flash memories&#44; where a single memory cell can hold numerous logic values&#46;</p><p id="par0030" class="elsevierStylePara elsevierViewall">In arithmetic circuits&#44; redundant number systems can reduce or even omit the rippling carries that leads to faster arithmetic operations as compared to the normal binary logic&#46; Moreover&#44; MVL can be even applied to solve the binary problems more effectively&#46; For instance&#44; a third logic value can be utilized as a medium for signaling the faulty operation in testing the binary circuits &#40;<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri&#44; Navi&#44; &#38; Hashemipour&#44; 2012b</a>&#41;&#46;</p><p id="par0035" class="elsevierStylePara elsevierViewall">Different methods for designing MVL circuits have been presented so far in the literature&#46; However&#44; most of them suffer from some critical drawbacks&#46; For instance&#44; the designs of &#40;<a class="elsevierStyleCrossRefs" href="#bib0080">Mouftah &#38; Jordan&#44; 1974&#59; Mouftah &#38; Smith&#44; 1982&#59; Raychowdhury &#38; Roy&#44; 2005</a>&#41; need very large resistors&#46; The CNTFET-based quaternary logic gates presented in &#40;<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al&#46;&#44; 2012b</a>&#41; function based on resistive voltage division at the output CNTFET stage which considerably increases the power consumption&#46; However&#44; the output drivers of these circuits enhance their drivability and considerably reduce the propagation delay&#46; Efficient multiple-valued logic gates have been presented in &#40;<a class="elsevierStyleCrossRef" href="#bib0045">Liang&#44; Chen&#44; Han&#44; &#38; Lombardi&#44; 2014</a>&#41; based on the pseudo n-type method which reduces the design complexity&#46; However&#44; the ratioed logic of the pseudo n-type method leads to higher propagation delay and power consumption and consequently less energy efficiency&#46; In addition&#44; it reduces the output logic swing that also increases the delay and static power consumption and degrades the robustness when these gates drive next stages&#46; Moreover&#44; in general&#44; each quaternary function can be implemented using quaternary multiplexers &#40;<a class="elsevierStyleCrossRef" href="#bib0010">Datla&#44; 2009</a>&#41;&#46; However&#44; purely multiplexer-based design does not result in a hardware-efficient circuit&#46;</p><p id="par0040" class="elsevierStylePara elsevierViewall">In this paper&#44; robust and energy-efficient CNTFET-based quaternary minimum and maximum circuits are designed for nanoelectronics based on an innovative combination of quaternary multiplexer&#44; threshold detectors and specific ternary buffers&#46;</p><p id="par0045" class="elsevierStylePara elsevierViewall">In the remainder of the paper&#44; in Section <a class="elsevierStyleCrossRef" href="#sec0010">2</a> the CNTFET device is briefly reviewed&#46; In Section <a class="elsevierStyleCrossRef" href="#sec0015">3</a> the proposed designs are presented&#46; The simulation results are represented in Section <a class="elsevierStyleCrossRef" href="#sec0020">4</a> and finally Section <a class="elsevierStyleCrossRef" href="#sec0025">5</a> concludes the paper&#46;</p></span><span id="sec0010" class="elsevierStyleSection elsevierViewall"><span class="elsevierStyleLabel">2</span><span class="elsevierStyleSectionTitle" id="sect0020">Carbon nanotube field effect transistor &#40;CNTFET&#41;</span><p id="par0050" class="elsevierStylePara elsevierViewall">Carbon nanotubes &#40;CNTs&#41; are graphite cylindrical sheets&#44; which are categorized into two groups&#58; single-walled carbon nanotubes &#40;SWCNTs&#41; that are made of a cylinder&#59; and multi-walled carbon nanotubes &#40;MWCNTs&#41; that are made of more than a cylinder &#40;<a class="elsevierStyleCrossRef" href="#bib0060">McEuen&#44; Fuhrer&#44; &#38; Park&#44; 2002</a>&#41;&#46; There is a chirality vector for any carbon nanotube&#44; which is specified by a pair &#40;<span class="elsevierStyleItalic">n</span>&#44; <span class="elsevierStyleItalic">m</span>&#41; and determines the angle of carbon atom formation along the nanotube&#46; Specifications of nanotubes depend on their structure and they can act as metal or semiconductor depending on the chirality&#46; If &#40;K&#8712;&#8484;&#41; <span class="elsevierStyleItalic">n</span><span class="elsevierStyleHsp" style=""></span>&#8722;<span class="elsevierStyleHsp" style=""></span><span class="elsevierStyleItalic">m</span><span class="elsevierStyleHsp" style=""></span>&#8800;<span class="elsevierStyleHsp" style=""></span>3<span class="elsevierStyleHsp" style=""></span>K&#44; the SWCNT is semiconductor and otherwise&#44; the SWCNT is metal&#46; SWCNTs are used instead of silicon bulk in the channel of transistors as the channel substance of CNTFET devices&#44; which reduces and sometimes removes many undesired parasitic elements&#46; Electrons and holes do not have an identical mobility in silicon whereas n-type and p-type CNTFETs have similar mobility &#40;<span class="elsevierStyleItalic">&#956;</span><span class="elsevierStyleInf">N</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span><span class="elsevierStyleItalic">&#956;</span><span class="elsevierStyleInf">p</span>&#41;&#46; This feature of CNTFETs facilitates the transistor sizing&#44; as the complexities will be fewer than the ones of MOSFET-based design&#46; CNTFET nanodevice has similar <span class="elsevierStyleItalic">I</span>&#8211;<span class="elsevierStyleItalic">V</span> characteristics as compared with a well-tempered MOSFET&#44; which is another advantage of CNTFETs &#40;<a class="elsevierStyleCrossRef" href="#bib0065">Moaiyeri&#44; Doostaregan&#44; &#38; Navi&#44; 2011</a>&#41;&#46;</p><p id="par0055" class="elsevierStylePara elsevierViewall">CNTFETs have three types including Schottky barrier CNTFET &#40;SB-CNTFET&#41;&#44; tunneling CNTFET &#40;T-CNTFET&#41; and MOSFET-like-CNTFET &#40;<a class="elsevierStyleCrossRef" href="#bib0095">Raychowdhury &#38; Roy&#44; 2007</a>&#41;&#46; However&#44; the MOSFET-like CNTFET is more suitable for designing circuits based on the CMOS style because of their inherent electrical characteristics and transistor structure&#46; Another feature of the MOSFET-like CNTFET is that drain&#47;source-channel connections have no Schottky barrier and it has a considerably higher ON current&#46; <a class="elsevierStyleCrossRef" href="#fig0005">Figure 1</a> shows a MOSFET-like CNTFET structure&#46;</p><elsevierMultimedia ident="fig0005"></elsevierMultimedia><p id="par0060" class="elsevierStylePara elsevierViewall">According to <a class="elsevierStyleCrossRef" href="#fig0005">Figure 1</a>&#44; the distance between the centers of two adjacent nanotubes is called pitch&#44; which has a direct impact on the width of the connections and gate of the transistor&#46; The width of the gate of a CNTFET is estimated by the following equation &#40;<a class="elsevierStyleCrossRef" href="#bib0040">Kim&#44; Kim&#44; &#38; Lombardi&#44; 2009</a>&#41;&#58;<elsevierMultimedia ident="eq0005"></elsevierMultimedia>where <span class="elsevierStyleItalic">N</span> is the number of nanotubes under the gate&#44; <span class="elsevierStyleItalic">W</span><span class="elsevierStyleInf">min</span> is the minimum width of the gate determined by the photolithography process and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">CNT</span> is the diameter of carbon nanotube&#44; which is calculated as given in Eq&#46; <a class="elsevierStyleCrossRef" href="#eq0010">&#40;2&#41;</a>&#44; where&#44; <span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#8776;<span class="elsevierStyleHsp" style=""></span>0&#46;249<span class="elsevierStyleHsp" style=""></span>nm is the lattice constant in a CNT structure &#40;<a class="elsevierStyleCrossRef" href="#bib0040">Kim et al&#46;&#44; 2009</a>&#41;&#58;<elsevierMultimedia ident="eq0010"></elsevierMultimedia></p><p id="par0075" class="elsevierStylePara elsevierViewall">The threshold voltage &#40;<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">th</span>&#41; of a CNTFET can be determined by adopting proper CNT diameters&#44; which is obtained from Eq&#46; <a class="elsevierStyleCrossRef" href="#eq0015">&#40;3&#41;</a> &#40;<a class="elsevierStyleCrossRef" href="#bib0040">Kim et al&#46;&#44; 2009</a>&#41;&#58;<elsevierMultimedia ident="eq0015"></elsevierMultimedia>where <span class="elsevierStyleItalic">e</span> is the unit electron charge&#44; <span class="elsevierStyleItalic">E</span><span class="elsevierStyleInf"><span class="elsevierStyleItalic">g</span></span> is the CNT band gap&#44; <span class="elsevierStyleItalic">E</span><span class="elsevierStyleInf"><span class="elsevierStyleItalic">&#960;</span></span> &#40;&#8776;3&#46;033<span class="elsevierStyleHsp" style=""></span>eV&#41; is the energy bond of carbon <span class="elsevierStyleItalic">&#960;</span>&#8211;<span class="elsevierStyleItalic">&#960;</span> in the tight bonding model&#46;</p><p id="par0085" class="elsevierStylePara elsevierViewall">Many feasible and effective approaches have already been presented in the literature for growing CNTs with a specified chirality and determining the desired threshold voltage for multi-tube CNTFETs &#40;<a class="elsevierStyleCrossRefs" href="#bib0050">Lin et al&#46;&#44; 2009&#59; Yang et al&#46;&#44; 2014</a>&#41;&#46; Nevertheless&#44; designing CNTFET-based circuits with fewer number of required CNT reduces fabrication costs and enhance the manufacturability&#46;</p></span><span id="sec0015" class="elsevierStyleSection elsevierViewall"><span class="elsevierStyleLabel">3</span><span class="elsevierStyleSectionTitle" id="sect0025">The proposed quaternary circuits</span><p id="par0090" class="elsevierStylePara elsevierViewall">As minimum &#40;logical multi-valued AND&#41; and max &#40;logical multi-valued OR&#41; operators are the most fundamental blocks of multiple valued logic systems&#44; an appropriate design of these two operators can be effective in enhancing the performance and energy-efficiency of MVL systems&#46; In this paper a new method for designing energy-efficient quaternary logic circuits is proposed&#46;</p><p id="par0095" class="elsevierStylePara elsevierViewall">The proposed method utilizes a quaternary 4-to-1 multiplexer &#40;QMux&#41; consisting of a selector &#40;generated by a quaternary decoder&#41; and a quaternary transmission gate network &#40;QTG&#41; and also threshold detector &#40;TD&#41; circuits&#46; An efficient design for CNTFET-based quaternary multiplexer has been presented in &#40;<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al&#46;&#44; 2012b</a>&#41;&#44; which is shown in <a class="elsevierStyleCrossRef" href="#fig0010">Figure 2</a>&#46;</p><elsevierMultimedia ident="fig0010"></elsevierMultimedia><p id="par0100" class="elsevierStylePara elsevierViewall"><a class="elsevierStyleCrossRef" href="#fig0015">Figure 3</a>&#40;a&#41; and &#40;b&#41; show the basic schema of the proposed quaternary minimum and maximum circuits&#44; respectively&#46; In these two circuits&#44; the QMux shown in <a class="elsevierStyleCrossRef" href="#fig0010">Figure 2</a> is used as the main body of the circuit&#46; The four inputs of the QMux circuits are assigned as per <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a>&#44; and accordingly the output of QMux1 will be the quaternary minimum signal &#40;QMin&#41; or the quaternary maximum signal &#40;QMax&#41;&#46;</p><elsevierMultimedia ident="fig0015"></elsevierMultimedia><elsevierMultimedia ident="tbl0005"></elsevierMultimedia><p id="par0105" class="elsevierStylePara elsevierViewall">As <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a> shows&#44; input <span class="elsevierStyleItalic">a</span> can be used as a selector in QMux1&#46; Therefore&#44; it is possible to divide the table into 4 sections based on different logic levels of <span class="elsevierStyleItalic">a</span> and adjust each input of QMux1 for each section of the table&#46; To adjust QMux1 input pins in QMin circuit&#44; we act as follows&#58;</p><p id="par0110" class="elsevierStylePara elsevierViewall">In the first section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#41;&#44; the QMin output has always a zero logic&#46; Therefore&#44; it is possible to connect the first QMux1 pin to zero logic without using any intermediate&#46;</p><p id="par0115" class="elsevierStylePara elsevierViewall">In the second section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#41;&#44; the QMin output has 0 and 1 logics&#46; According to the table&#44; if <span class="elsevierStyleItalic">b</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#44; QMin equals 0&#46; Otherwise &#40;<span class="elsevierStyleItalic">b</span><span class="elsevierStyleHsp" style=""></span>&#8800;<span class="elsevierStyleHsp" style=""></span>0&#41;&#44; QMin equals to 1&#46; Therefore&#44; an nMOS-based threshold detector &#40;TDN&#41; module can be used&#44; which is switched on logical &#8216;0&#46;5&#8217; and is controlled by the input signal <span class="elsevierStyleItalic">b</span> through the inverters &#40;<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al&#46;&#44; 2012b</a>&#41;&#46; <a class="elsevierStyleCrossRef" href="#fig0020">Figure 4</a> shows the nMOS-based TD circuit&#46;</p><elsevierMultimedia ident="fig0020"></elsevierMultimedia><p id="par0120" class="elsevierStylePara elsevierViewall">In the third section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>2&#41;&#44; QMin output has 0&#44; 1&#44; 2 and 2 logics&#44; respectively&#46; In order to realize these logics in the third QMux1 input pin&#44; another multiplexer &#40;QMux2&#41; with input selector <span class="elsevierStyleItalic">b</span> can be used&#46; Accordingly&#44; the inputs of QMux2 should be connected to 0&#44; 1&#44; 2&#44; 2 logics&#46;</p><p id="par0125" class="elsevierStylePara elsevierViewall">In the fourth section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>3&#41;&#44; the QMin output is similar to input <span class="elsevierStyleItalic">b</span>&#46; Therefore&#44; it is possible to connect the fourth QMux1 input pin to the input <span class="elsevierStyleItalic">b</span> without using any intermediate&#46;</p><p id="par0130" class="elsevierStylePara elsevierViewall">To adjust QMux1 input pins in maximum circuit&#44; we act as follows&#58;<ul class="elsevierStyleList" id="lis0005"><li class="elsevierStyleListItem" id="lsti0005"><p id="par0135" class="elsevierStylePara elsevierViewall">In the first section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#41;&#44; the QMax output is similar to input <span class="elsevierStyleItalic">b</span>&#46; Therefore&#44; it is possible to connect the first QMux1 pin to the input b without using any intermediate&#46;</p></li><li class="elsevierStyleListItem" id="lsti0010"><p id="par0140" class="elsevierStylePara elsevierViewall">In the second section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#41;&#44; the QMax output has 1&#44; 1&#44; 2 and 3 logics&#44; respectively&#46; To realize these logics in the second input of QMux1&#44; another multiplexer &#40;QMux2&#41; with a <span class="elsevierStyleItalic">b</span> input selector can be used&#46; Inputs of the multiplexer can be respectively connected to 1&#44; 1&#44; 2 and 3 logics&#46;</p></li><li class="elsevierStyleListItem" id="lsti0015"><p id="par0145" class="elsevierStylePara elsevierViewall">In the third section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>2&#41;&#44; QMax output has 2 and 3 logics&#46; As <a class="elsevierStyleCrossRef" href="#tbl0005">Table 1</a> shows&#44; for <span class="elsevierStyleItalic">b</span><span class="elsevierStyleHsp" style=""></span>&#8800;<span class="elsevierStyleHsp" style=""></span>3&#44; the output of QMax equals to logic 2 and for input <span class="elsevierStyleItalic">b</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>3&#44; output logic equals to 3&#46; Therefore&#44; a pMOS-based TD &#40;TDP&#41; module can be used&#44; which switches on logic &#8216;2&#46;5&#8217; and controlled by the input signal <span class="elsevierStyleItalic">b</span> through the inverters&#46; <a class="elsevierStyleCrossRef" href="#fig0025">Figure 5</a> shows the proposed pMOS-based TD&#46;</p><elsevierMultimedia ident="fig0025"></elsevierMultimedia></li><li class="elsevierStyleListItem" id="lsti0020"><p id="par0150" class="elsevierStylePara elsevierViewall">In the fourth section &#40;<span class="elsevierStyleItalic">a</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>3&#41;&#44; QMax output has always logic 3&#46; Therefore&#44; it is possible to connect the fourth QMux1 pin to logic 3 without using any intermediate&#46;</p></li></ul></p><p id="par0155" class="elsevierStylePara elsevierViewall">The proposed design can be simplified more by removing the QMux2 module used in the second pin of maximum circuit and the third pin of minimum circuit and replacing each of them by another circuit in order to reach a more hardware-efficient circuit with higher performance&#46; Therefore&#44; two ternary buffer circuits are designed&#44; which can help to achieve the desired outputs with lower number of transistors&#46; As the QMux2 module has been utilized with different inputs in the basic schemas of the proposed minimum and maximum circuits&#44; two different ternary buffers should be used in the second design for minimum and maximum circuits&#46; The main difference between these two buffers is their different required switching thresholds which are obtained by adopting proper diameters in the first level inverters of the buffers&#46;</p><p id="par0160" class="elsevierStylePara elsevierViewall"><a class="elsevierStyleCrossRef" href="#fig0030">Figure 6</a> shows the final proposed minimum circuit and the transistor level schema of its ternary buffer &#40;TB1&#41;&#46; This circuit includes specific CMOS-like threshold detector inverters and a voltage division stage according to &#40;<a class="elsevierStyleCrossRef" href="#bib0065">Moaiyeri et al&#46;&#44; 2011</a>&#41;&#46; It is worth pointing out that in the proposed TB1 circuit <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">N</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#46;018<span class="elsevierStyleHsp" style=""></span>nm and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">P</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#46;487<span class="elsevierStyleHsp" style=""></span>nm are adopted for the diameters of the n-type and p-type devices in inverter1 and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">N</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#46;487<span class="elsevierStyleHsp" style=""></span>nm and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">P</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#46;783<span class="elsevierStyleHsp" style=""></span>nm are adopted in inverter2&#46; In addition&#44; a 2&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span> &#40;a 2 logical level&#41; voltage is utilized as the supply in this circuit&#46; Accordingly&#44; the required 0&#44; 1&#44; 2 logics are obtained at the output of TB1 in the proposed minimum circuit&#46;</p><elsevierMultimedia ident="fig0030"></elsevierMultimedia><p id="par0165" class="elsevierStylePara elsevierViewall">The voltage transfer characteristic &#40;VTC&#41; curve of the ternary buffer used in the proposed QMin circuit is illustrated in <a class="elsevierStyleCrossRef" href="#fig0035">Figure 7</a>&#46; As demonstrated in <a class="elsevierStyleCrossRef" href="#fig0035">Figure 7</a>&#44; the proposed buffer produces the desired output voltage levels including 0&#44; 1&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span> and 2&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span> &#40;<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#46;8<span class="elsevierStyleHsp" style=""></span>V&#41;&#46; In addition&#44; it has a near-ideal VTC with quite steep transition regions which enhance the robustness of the design&#46;</p><elsevierMultimedia ident="fig0035"></elsevierMultimedia><p id="par0170" class="elsevierStylePara elsevierViewall"><a class="elsevierStyleCrossRef" href="#fig0040">Figure 8</a> shows the final proposed maximum circuit and the transistor level schema of its ternary buffer &#40;TB2&#41;&#46; It is worth pointing out that by selecting <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">N</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#46;487<span class="elsevierStyleHsp" style=""></span>nm and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">P</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#46;783<span class="elsevierStyleHsp" style=""></span>nm for the diameters of the n-type and p-type devices in Inverter1 and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">N</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>0&#46;783<span class="elsevierStyleHsp" style=""></span>nm and <span class="elsevierStyleItalic">D</span><span class="elsevierStyleInf">P</span><span class="elsevierStyleHsp" style=""></span>&#61;<span class="elsevierStyleHsp" style=""></span>1&#46;018<span class="elsevierStyleHsp" style=""></span>nm in Inverter2 and using a 1&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span> supply &#40;a 1 logical value&#41; as the lowest voltage level&#44; the required 1&#44; 2&#44; 3 logics are obtained in TB2 of the maximum circuit&#46;</p><elsevierMultimedia ident="fig0040"></elsevierMultimedia><p id="par0175" class="elsevierStylePara elsevierViewall">The voltage transfer characteristic curve of the ternary buffer used in the proposed QMax circuit is shown in <a class="elsevierStyleCrossRef" href="#fig0045">Figure 9</a>&#46; As illustrated in <a class="elsevierStyleCrossRef" href="#fig0045">Figure 9</a>&#44; the proposed buffer produces the desired output voltage levels including 1&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span>&#44; 2&#47;3<span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span> and <span class="elsevierStyleItalic">V</span><span class="elsevierStyleInf">DD</span>&#46; In addition&#44; it has a near-ideal VTC with quite steep transition regions which enhance the robustness of the design&#46;</p><elsevierMultimedia ident="fig0045"></elsevierMultimedia></span><span id="sec0020" class="elsevierStyleSection elsevierViewall"><span class="elsevierStyleLabel">4</span><span class="elsevierStyleSectionTitle" id="sect0030">Simulation results and comparison</span><p id="par0180" class="elsevierStylePara elsevierViewall">This section discusses the performance of the proposed circuits in different conditions using Synopsys HSPICE with the Stanford compact model CNTFET including all the possible non-idealities at 32<span class="elsevierStyleHsp" style=""></span>nm technology node&#46; This standard model has been developed for unipolar enhancement-mode MOSFET-like-CNTFET&#44; devices in which each transistor may include one or more CNTs as its channel&#46; This model considers the following items idealistically&#46; The Schottky barrier effects at the contacts&#44; inter-CNT charge screening effects&#44; scattering&#44; back-gate effect&#44; gate and source&#47;drain resistances and expansion of doped regions of source&#47;drain &#40;<a class="elsevierStyleCrossRefs" href="#bib0015">Deng&#44; 2007&#59; Deng &#38; Wong&#44; 2007a&#44; 2007b</a>&#41;&#46; <a class="elsevierStyleCrossRef" href="#tbl0010">Table 2</a> shows CNTFET model parameters&#44; their values&#44; and a brief explanation&#46;</p><elsevierMultimedia ident="tbl0010"></elsevierMultimedia><p id="par0185" class="elsevierStylePara elsevierViewall"><a class="elsevierStyleCrossRef" href="#fig0050">Figure 10</a> shows the input and output signals of the proposed quaternary logic circuits simulated at 0&#46;8<span class="elsevierStyleHsp" style=""></span>V supply voltage&#44; which authenticates the correct operation of the designs&#46;</p><elsevierMultimedia ident="fig0050"></elsevierMultimedia><p id="par0190" class="elsevierStylePara elsevierViewall">The proposed CNTFET-based quaternary circuits are simulated at 0&#46;8<span class="elsevierStyleHsp" style=""></span>V supply voltage with a 0&#46;5<span class="elsevierStyleHsp" style=""></span>fF load capacitor and the results including propagation delay&#44; power consumption&#44; power-delay product &#40;PDP&#41; and energy-delay product &#40;EDP&#41; are given in <a class="elsevierStyleCrossRef" href="#tbl0015">Table 3</a>&#46; According to the results&#44; the proposed designs have smaller propagation delays as compared to &#40;<a class="elsevierStyleCrossRef" href="#bib0045">Liang et al&#46;&#44; 2014</a>&#41;&#44; lower power consumption in comparison with &#40;<a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri et al&#46;&#44; 2012b</a>&#41; and the lowest PDP and EDP values&#46;</p><elsevierMultimedia ident="tbl0015"></elsevierMultimedia><p id="par0195" class="elsevierStylePara elsevierViewall">Moreover&#44; the proposed designs are simulated at different ambient temperatures from 0 to 90<span class="elsevierStyleHsp" style=""></span>&#176;C in order to evaluate their operation at different temperatures&#46; The PDP of a CNTFET-based circuit usually does not change significantly by temperature variations because of CNT thermal stability&#46; In addition&#44; as shown in <a class="elsevierStyleCrossRef" href="#fig0055">Figure 11</a>&#44; the proposed designs have lower PDP at different temperatures as compared to the other designs&#46;</p><elsevierMultimedia ident="fig0055"></elsevierMultimedia><p id="par0200" class="elsevierStylePara elsevierViewall">Systematic and random process variations are among the major challenges ahead of nanoscale devices and circuits&#46; As the proposed CNTFET-based quaternary logic circuits are designed based on multiple threshold voltage method&#44; the impact of the process variation that alternates the threshold voltage of the CNTFETs should be definitely studied&#46; As the proposed method is based on multi threshold CNTFETs and the threshold voltage of a CNTFET is dominantly determined by the diameter of its CNTs&#44; the functionality of the proposed quaternary circuit should be evaluated considering CNT diameter variations&#46; In addition&#44; recently&#44; CNT counts variations is proven experimentally to be the most important source of variation in CNTFET circuits &#40;<a class="elsevierStyleCrossRef" href="#bib0110">Zhang&#44; Patil&#44; Wong&#44; &#38; Mitra&#44; 2011</a>&#41;&#46;</p><p id="par0205" class="elsevierStylePara elsevierViewall">Therefore&#44; the Monte Carlo simulation has been carried out to assess these process variations with &#177;5&#37; up to &#177;15&#37; Gaussian distributions and variation at the &#177;3<span class="elsevierStyleItalic">&#963;</span> level&#46; <a class="elsevierStyleCrossRef" href="#fig0060">Figure 12</a> shows the results of this simulation&#46; According to the results&#44; the proposed CNTFET-based logic circuits are very low sensitive to process variations&#44; especially in terms of power variations&#46;</p><elsevierMultimedia ident="fig0060"></elsevierMultimedia></span><span id="sec0025" class="elsevierStyleSection elsevierViewall"><span class="elsevierStyleLabel">5</span><span class="elsevierStyleSectionTitle" id="sect0035">Conclusions</span><p id="par0210" class="elsevierStylePara elsevierViewall">As the nanotechnology-based multiple-valued logic design is concerned&#44; energy-efficient min&#8211;max circuits have been proposed based on CNTFETs with multi threshold voltages based on the CNTFET&#39;s unique properties&#46; The simulation results certify authenticity of the proposed method as a superior proposed quaternary minimum and maximum circuit&#44; especially in terms of PDP and EDP&#44; as compared with other circuits under different simulation conditions and in the presence of process and temperature variations&#46; The proposed designs leads to 51&#37; and 63&#37; lower PDP and 64&#37; and 61&#37; lower EDP&#44; respectively as compared to the state-of-the-art CNTFET-based quaternary circuits presented in the literature&#46; In future work we expect to develop the proposed method for implementing complex arithmetic operations and designing an efficient quaternary ALU&#46; Also&#44; we expect that the proposed method can be generalized effectively for radices higher than four&#46;</p></span><span id="sec0070" class="elsevierStyleSection elsevierViewall"><span class="elsevierStyleSectionTitle" id="sect0040">Conflict of interest</span><p id="par0575" class="elsevierStylePara elsevierViewall">The authors have no conflicts of interest to declare&#46;</p></span></span>"
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          "titulo" => "Introduction"
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        3 => array:2 [
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          "titulo" => "Carbon nanotube field effect transistor &#40;CNTFET&#41;"
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    "fechaRecibido" => "2015-07-31"
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        "titulo" => "Abstract"
        "resumen" => "<span id="abst0005" class="elsevierStyleSection elsevierViewall"><p id="spar0005" class="elsevierStyleSimplePara elsevierViewall">This article presents energy-efficient quaternary minimum and maximum logic circuits based on carbon nanotube field-effect transistor &#40;CNTFET&#41;&#46; The specific features of CNTFET&#44; such as the possibility of determining the desired threshold voltages which are obtained by acquiring suitable diameters for carbon nanotubes&#44; facilitate designing efficient circuits with multiple threshold voltages&#46; The proposed minimum and maximum circuits are designed using an efficient combination of quaternary multiplexers and specific ternary buffers&#46; The proposed designs are simulated using Synopsys HSPICE with the Stanford 32<span class="elsevierStyleHsp" style=""></span>nm CNTFET technology and the performance parameters and sensitivity to process and temperature variations are evaluated through comprehensive simulations&#46; The results demonstrate that the proposed QMin and QMax designs operate with high robustness even in the presence of major process variations&#46; In addition&#44; they have 51&#37; and 63&#37; lower power-delay product &#40;PDP&#41; and 64&#37; and 61&#37; lower energy-delay product &#40;EDP&#41;&#44; respectively&#44; as compared to the state-of-the-art CNTFET-based quaternary circuits recently presented in the literature&#46;</p></span>"
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                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " colspan="4" align="left" valign="top"><span class="elsevierStyleVsp" style="height:0.5px"></span></td></tr><tr title="table-row"><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr></tbody></table>
                  """
              ]
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                0 => "xTab1446118.png"
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          "en" => "<p id="spar0070" class="elsevierStyleSimplePara elsevierViewall">The truth table of the QMin and QMax operations&#46;</p>"
        ]
      ]
      13 => array:8 [
        "identificador" => "tbl0010"
        "etiqueta" => "Table 2"
        "tipo" => "MULTIMEDIATABLA"
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              "tabla" => array:1 [
                0 => """
                  <table border="0" frame="\n
                  \t\t\t\t\tvoid\n
                  \t\t\t\t" class=""><thead title="thead"><tr title="table-row"><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Parameter&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Brief description&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Value&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th></tr></thead><tbody title="tbody"><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">ch</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">Physical channel length&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">32<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">ss</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The length of doped CNT source-side extension region&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">32<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">dd</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The length of doped CNT drain-side extension region&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">32<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">geff</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The Scattering mean free path in the intrinsic CNT channel and S&#47;D regions&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">100<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Pitch&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The distance between the centers of two neighboring CNTs within the same device&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">20<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">eff</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The mean free path in p&#43;&#47;n&#43; doped CNT&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">15<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Sub&#95;pitch&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">Sub-lithographic &#40;e&#46;g&#46; CNT gate width&#41; pitch&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">4<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">K</span><span class="elsevierStyleInf">ox</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The dielectric constant of high-k top gate dielectric material&#40;HfO<span class="elsevierStyleInf">2</span>&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">16&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">L</span><span class="elsevierStyleInf">ox</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The thickness of high-k top gate dielectric material&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">4<span class="elsevierStyleHsp" style=""></span>nm&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">K</span><span class="elsevierStyleInf">sub</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The dielectric constant of substrate &#40;SiO<span class="elsevierStyleInf">2</span>&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">4&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleItalic">C</span><span class="elsevierStyleInf">sub</span>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The coupling capacitance between the channel region and the substrate &#40;SiO<span class="elsevierStyleInf">2</span>&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">40<span class="elsevierStyleHsp" style=""></span>aF&#47;&#956;m&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Efi&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The Fermi level of the doped S&#47;D tube&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">6<span class="elsevierStyleHsp" style=""></span>eV&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Phi&#95;M&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">The work function of source&#47;drain metal contact&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">4&#46;6<span class="elsevierStyleHsp" style=""></span>eV&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top">Phi&#95;S&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">CNT work function&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="left" valign="top">4&#46;5<span class="elsevierStyleHsp" style=""></span>eV&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr></tbody></table>
                  """
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          "en" => "<p id="spar0075" class="elsevierStyleSimplePara elsevierViewall">Some of the important CNTFET model parameters&#46;</p>"
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                0 => """
                  <table border="0" frame="\n
                  \t\t\t\t\tvoid\n
                  \t\t\t\t" class=""><thead title="thead"><tr title="table-row"><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Designs&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Delay &#40;10<span class="elsevierStyleSup">&#8722;12</span><span class="elsevierStyleHsp" style=""></span>s&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">Power &#40;10<span class="elsevierStyleSup">&#8722;6</span><span class="elsevierStyleHsp" style=""></span>W&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">PDP &#40;10<span class="elsevierStyleSup">&#8722;16</span><span class="elsevierStyleHsp" style=""></span>J&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th><th class="td" title="table-head  " align="left" valign="top" scope="col" style="border-bottom: 2px solid black">EDP &#40;10<span class="elsevierStyleSup">&#8722;27</span><span class="elsevierStyleHsp" style=""></span>Js&#41;&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</th></tr></thead><tbody title="tbody"><tr title="table-row"><td class="td" title="table-entry  " colspan="5" align="left" valign="top"><span class="elsevierStyleItalic">QMin</span></td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Proposed design&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">35&#46;91&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&#46;401&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;503&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&#46;806&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Design of <a class="elsevierStyleCrossRef" href="#bib0045">Liang et al&#46; &#40;2014&#41;</a>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">138&#46;1&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;451&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;623&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">8&#46;601&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Design of <a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri&#44; Navi&#44; et al&#46; &#40;2012b&#41;</a>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">11&#46;96&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">24&#46;57&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&#46;931&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">3&#46;504&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td" title="table-entry  " colspan="5" align="left" valign="top"><span class="elsevierStyleVsp" style="height:0.5px"></span></td></tr><tr title="table-row"><td class="td" title="table-entry  " colspan="5" align="left" valign="top"><span class="elsevierStyleItalic">QMax</span></td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Proposed design&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">32&#46;44&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&#46;350&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;436&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">1&#46;414&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Design of <a class="elsevierStyleCrossRef" href="#bib0045">Liang et al&#46; &#40;2014&#41;</a>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">130&#46;8&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;621&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">0&#46;811&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">10&#46;61&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr><tr title="table-row"><td class="td-with-role" title="table-entry ; entry_with_role_rowhead " align="left" valign="top"><span class="elsevierStyleHsp" style=""></span>Design of <a class="elsevierStyleCrossRef" href="#bib0075">Moaiyeri&#44; Navi&#44; et al&#46; &#40;2012b&#41;</a>&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">9&#46;741&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">24&#46;58&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&#46;239&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td><td class="td" title="table-entry  " align="char" valign="top">2&#46;181&nbsp;\t\t\t\t\t\t\n
                  \t\t\t\t</td></tr></tbody></table>
                  """
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          "en" => "<p id="spar0080" class="elsevierStyleSimplePara elsevierViewall">Simulation result of quaternary maximum and minimum circuits&#46;</p>"
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      ]
      15 => array:6 [
        "identificador" => "eq0005"
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Article information

ISSN: 16656423
Original language: English

DOI:10.1016/j.jart.2016.12.006

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Year/Month	Html	Pdf	Total

2024 October	29	5	34
2024 September	43	1	44
2024 August	44	0	44
2024 July	42	13	55
2024 June	49	6	55
2024 May	33	7	40
2024 April	42	8	50
2024 March	47	15	62
2024 February	47	7	54
2024 January	46	11	57
2023 December	61	20	81
2023 November	73	12	85
2023 October	108	16	124
2023 September	54	6	60
2023 August	53	5	58
2023 July	52	8	60
2023 June	84	6	90
2023 May	99	17	116
2023 April	63	5	68
2023 March	75	12	87
2023 February	65	4	69
2023 January	57	7	64
2022 December	55	9	64
2022 November	52	6	58
2022 October	41	9	50
2022 September	50	11	61
2022 August	59	13	72
2022 July	47	18	65
2022 June	40	8	48
2022 May	40	13	53
2022 April	46	12	58
2022 March	89	16	105
2022 February	76	15	91
2022 January	80	13	93
2021 December	70	17	87
2021 November	60	19	79
2021 October	55	8	63
2021 September	34	18	52
2021 August	38	5	43
2021 July	53	12	65
2021 June	52	15	67
2021 May	57	13	70
2021 April	109	36	145
2021 March	48	30	78
2021 February	22	7	29
2021 January	35	15	50
2020 December	40	9	49
2020 November	63	11	74
2020 October	50	6	56
2020 September	22	7	29
2020 August	25	2	27
2020 July	25	6	31
2020 June	30	3	33
2020 May	23	6	29
2020 April	23	3	26
2020 March	18	6	24
2020 February	22	8	30
2020 January	21	8	29
2019 December	25	8	33
2019 November	23	11	34
2019 October	30	4	34
2019 September	47	14	61
2019 August	35	11	46
2019 July	30	17	47
2019 June	72	24	96
2019 May	143	50	193
2019 April	85	21	106
2019 March	13	8	21
2019 February	22	5	27
2019 January	21	8	29
2018 December	13	8	21
2018 November	24	5	29
2018 October	43	7	50
2018 September	38	6	44
2018 August	17	6	23
2018 July	21	6	27
2018 June	18	3	21
2018 May	29	13	42
2018 April	16	4	20
2018 March	22	2	24
2018 February	24	3	27
2018 January	20	3	23
2017 December	9	3	12
2017 November	22	2	24
2017 October	17	11	28
2017 September	12	6	18
2017 August	37	7	44
2017 July	39	12	51
2017 June	5	6	11
2017 May	1	7	8
2017 April	0	1	1

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